Network Interconnect for Exascale Systems

Network: the next big bottleneck?

Network interconnect is the backbone of a supercomputer, connecting together the compute nodes

To reach the exascale with a reasonable power consumption, exascale supercomputers will include a huge number of nodes, and they will be hybrid nodes integrating GPUs and CPUs

Integrating heterogeneous nodes requires a smarter interconnect, with additional features to accelerate connectivity between servers and storage

Those are the challenges that RED-SEA is tackling to design the network interconnect that will power future European Exascale systems

The RED-SEA blog

By the RED-SEA experts

Latest blog

  • Low-latency Communication in RISC-V Clusters
    Authors: Charisios Loukas, Evangelos Mageiropoulos and Nikos Chrysos, FORTH Don’t miss the demo at the end of this article! Low-latency inter-node communication is important in HPC clusters. Following the conclusion of the ExaNeSt project, which studied the adoption of low-cost, power-efficient Arm processor clusters for Exascale-class systems, as part of the RED-SEA project, we swapped the Arm processors for RISC-V. In this work, we tightly coupled a lean, low-latency network interface with a modified Ariane RISC-V soft core. Hardware Testbed Our system, shown in Figure 1, consists of 2 TE0808 Trenz boards, each equipped with a XCZU9 Xilinx MPSoC, with… Read more: Low-latency Communication in RISC-V Clusters



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Our partners the other SEA projects

The EuroHPC projects DEEP-SEA, IO-SEA and RED-SEA have joined forces to develop complementary European technologies for future heterogeneous exascale supercomputing architectures.

An introduction to the Modular Supercomputing Architecture leveraged by the SEA projects: