About the project

Context

Network interconnects play an enabling role in HPC systems – and this will be even truer for the coming Exascale systems that will rely on higher node counts and increased use of parallelism and communication. Moreover, next-generation HPC and data-driven systems will be powered by heterogeneous computing devices, including low-power Arm and RISC-V processors, high-end CPUs, vector acceleration units and GPUs suitable for massive single-instruction multiple-data (SIMD) workloads, as well as FPGA and ASIC designs tailored for extremely power-efficient custom codes.

Network: the next big bottleneck?

These compute units will be surrounded by distributed, heterogeneous (often deep) memory hierarchies, including high-bandwidth memories and fast devices offering microsecond-level access time. At the same time, modern data-parallel processing units such as GPUs and vector accelerators can crunch data at amazing rates (tens of TFLOPS). In this landscape, the network may well become the next big bottleneck, similar to memory in single node systems.

RED-SEA prepares a new-generation network interconnect to power the future EU Exascale systems

RED-SEA will build upon the European interconnect BXI (BullSequana eXascale Interconnect), together with standard and mature technology (Ethernet) and previous EU-funded initiatives to provide a competitive and efficient network solution for the exascale era and beyond. This involves developing the key IPs and the software environment that will deliver:

  • scalability, while maintaining an acceptable total cost of ownership and power efficiency;
  • virtualization and security, to allow various applications to efficiently and safely share an HPC system;
  • Quality-of-service and congestion management to make it possible to share the platform among users and applications with different demands;
  • reliability at scale, because fault tolerance is a key concern in a system with a very large number of components;
  • support of high-bandwidth low-latency HPC Ethernet, as HPC systems increasingly need to interact securely with the outside world, including public clouds, edge servers or third party HPC systems;
  • support of heterogeneous programming model and runtimes to facilitate the convergence of HPC and HPDA;
  • support for low-power processors and accelerators.

RED-SEA in the Modular Supercomputing Architecture

RED-SEA supports the Modular Supercomputing Architecture (MSA) that underpins all of the SEA projects. In the MSA, BXI is the HPC fabric within each compute module, delivering low-latency, high bandwidth and all required HPC features, whereas Ethernet is the high-performance federative network that offers interface to storage and with other compute modules. RED-SEA will design a seamless interface between BXI and Ethernet via a new Gateway solution.

Objectives

Enable

Enable the design of a new generation of high performance network interconnect

  • Leveraging existing European technology (BXI, Exanest …)
  • Able  to power the future EU Exascale systems

Explore

Explore new innovative solutions

End-to-end network services – from programming models to reliability, security, low latency, and new processors

Develop

Develop the ecosystem and create a broader community of users and developers

Leveraging open standard and compatible API to develop innovative re-useable libraries and Fabrics management solutions

The RED-SEA network architecture

Partners

A consortium gathering academia and industry

The RED-SEA project is coordinated by Atos, and brings together the top European academic centres and the key European industrial forces in the domain of interconnect networks. The RED-SEA consortium gathers 12 partners from 6 countries.

Factsheet

Project nameNetwork Solution for Exascale Architectures
Project acronymRED-SEA
Project typeEuroHPC-RIA
Project start01/04/2021
Project end31/03/2024
CallH2020-JTI-EuroHPC-2019-1
Grant agreement955776
CoordinatorAtos (Bull SAS)
Total budget€ 7 993 710
EU funding€ 3 996 855,01

Deliverables

  • D2.3 RoCE and IPoverBXI Evaluation Report
    Edited by Nikolaos D. Kallimanis (FORTH), Gregoire Pichon (Atos) Authors Giorgos Saloustros (FORTH), Nikolaos D. Kallimanis (FORTH), Nikolaos Chrysos (FORTH), Jonathan Espié Caullet (Atos), Sylvain Goudeau (Atos), Grégoire Pichon (Atos) Executive summary In the RED-SEA […]
  • D4.3 Planned MPI-related optimizations
    Edited by Hugo Taboada (CEA) Authors Gilles Moreau (CEA), Hugo Taboada (CEA), Marc Pérache (CEA), Simon Pickartz (ParTec), Carsten Clauss (ParTec) Executive summary This document presents the two contributions from Commissariat à l’énergie atomique et […]

Publications